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LTC1329-10/ LTC1329-50/LTC1329A-50 Micropower 8-Bit Current Output D/A Converter
FEATURES
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DESCRIPTION
The LTC (R)1329-10/LTC1329-50/LTC1329A-50 are micropower 8-bit current output D/A converters (DACs) with an output range of 0A to 10A for the LTC1329-10 and 0A to 50A for the LTC1329-50/LTC1329A-50. The DAC current output can be biased from - 15V to 2V or - 15V to 2.5V in 3.3V and 5V systems, respectively. Supply current is only 95A for the LTC1329-50/LTC1329A-50 and 75A for LTC1329-10. A shutdown mode drops the supply current to 0.2A. The LTC1329 can communicate with external circuitry by using one of three interface modes: standard 3-wire serial mode and two pulse modes. Upon power-up, the internal counter resets to 1000 0000B, the DAC output assumes midrange and the chip is configured in 3-wire or pulse mode depending on the signal level at CS. In 3-wire mode, the system MPU can serially transfer 8-bit data to and from the LTC1329. In pulse mode, the upper six bits of the DAC output can be programmed for increment-only (1-wire interface) or increment/decrement (2-wire interface) operation depending on the signal level at DIN. LTC1329 is available in 8-pin SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. Triple Mode is a trademark of Linear Technology Corporation.
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Guaranteed Precision Full-Scale DAC Output Current at 25C: LTC1329A-50 50A 1% LTC1329-10 10A 3% LTC1329-50 50A 3% Wide Output Voltage DC Compliance: - 15V to 2.5V Wide Supply Range: 2.7V VCC 6.5V Supply Current in Shutdown: 0.2A Low Supply Current: 75A for LTC1329-10, 95A for LTC1329-50/LTC1329A-50 Available in 8-Pin SO Triple ModeTM Interface Modes 1. Standard 3-Wire Mode 2. Pulse Mode 1-Wire Interface: Increment-Only 3. Pulse Mode 2-Wire Interface: Increment/Decrement Can Read Back the 8-Bit DAC Value in 3-Wire Mode DAC Powers Up at Midrange DAC Contents Are Retained in Shutdown
APPLICATIONS
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LCD Contrast Control Backlight Brightness Control Battery Charger Current/Voltage Adjustment Power Supply Voltage Adjustment Trimmer Pot Elimination
TYPICAL APPLICATION
Digitally Controlled LCD Bias Generator
VIN 5V 47 VIN SW1 LT (R)1173 FB GND SW2 1N5818 ILIM L1* 100H
1N4148
200k
0.1F 1 2 IOUT VCC DOUT DIN 8 7 MPU (e.g., 8051)
+
47F
+
4.7F 10.1k 1N5818
LTC1329-50 3 4 SHDN CLK GND CS 6 5
+
22F *GOWANDA GA10-103K OR COILTRONICS CTX100-4
220k VOUT -22V at 40mA
1329 TA01
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P1.2 P1.1 P1.0
1
LTC1329-10/ LTC1329-50/LTC1329A-50
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW IOUT 1 VCC 2 SHDN 3 CLK 4 8 DOUT 7 DIN (UP/DN) 6 GND 5 CS
Supply Voltage (VCC) ................................................ 7V Input Voltage (All Inputs)............ - 0.3V to (VCC + 0.3V) Output Voltage IOUT ......................................... - 15V to (VCC + 0.3V) DOUT ....................................... - 0.3V to (VCC + 0.3V) Short-Circuit Duration (All Outputs) ............... Indefinite Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1329CS8-10 LTC1329CS8-50 LTC1329ACS8-50 S8 PART MARKING 13291 1329A5 13295
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 150C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VCC ICC Supply Current CONDITIONS
VCC = 3.3V, TA = 25C, unless otherwise specified.
LTC1329-10 MIN TYP MAX 2.7 6.5 75 130 0.2 8 10 10 5 10.3 10.5 48.5 47.5 49.5 49.0 LTC1329-50/LTC1329A-50 MIN TYP MAX 2.7 6.5 95 150 0.2 8 50 50 50 50 5 51.5 52.5 50.5 51.0 200 0.9 2 4 0.25 1.5 1 2.0 1.9 0.80 0.45 2.4 2.1 0.4 0.4 5 2.4 2.1 0.4 0.4 5 0.80 0.45 UNITS V A A Bits A A A A nA LSB LSB LSB LSB LSB A V V V V V V V V A
q
VSHDN = VDIN = VCS = VCC, VCLK = 0V, DOUT = NC, IOUT = NC Shutdown Output Voltage at IOUT = 0.45V, TA = 25C (LTC1329-10, LTC1329-50) Output Voltage at IOUT = 0.45V, TA = 25C (LTC1329A-50) Output Voltage at IOUT = 0.45V Monotonicity Guaranteed
q q
DAC Resolution DAC Full-Scale Current
q q q q q q q q q q q q q q q q q q
9.7 9.5
IIH, IIL VIH VIL VOH VOL IOZ
VCC = 3V to 5.5V, IOUT = Full Scale, Output Voltage at IOUT = 0.45V VCC = 2.7V to 6.5V, Full Scale, Output Voltage at IOUT = 0.45V Output Voltage Rejection VCC = 5V, IOUT = Full Scale, Output Voltage at IOUT = - 15V to 0V VCC = 5V, IOUT = Full Scale, Output Voltage at IOUT = 0V to 2.5V Logic Input Current 0V VIN VCC High Level Input Voltage VCC = 5V VCC = 3.3V Low Level Input Voltage VCC = 5V VCC = 3.3V High Level Output Voltage VCC = 5V, IO = 400A VCC = 3.3V, IO = 400A Low Level Output Voltage VCC = 5V, IO = 2mA VCC = 3.3V, IO = 1mA Three-State Output Leakage VCS = VCC
DAC Zero-Scale Current DAC Differential Nonlinearity Supply Voltage Rejection
0.3 1 2.5 0.25
200 0.9 2 4 1 1.5 1 1 2.5
2.0 1.9
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WW
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LTC1329-10/ LTC1329-50/LTC1329A-50
RECO
fCLK tCKS tCSS tDV tDS tDH tDO tCKHI tCKLO tCSH tDZ tCKH tCSLO tCSHI
E DED OPERATI G CO DITIO S
CONDITIONS
SYMBOL PARAMETER Serial Interface Clock Frequency Setup Time, CLK Before CS Setup Time, CS Before CLK CS to DOUT Valid DIN Setup Time Before CLK DIN Hold Time After CLK CLK to DOUT Valid CLK High Time CLK Low Time CLK Before CS CS to DOUT in Hi-Z CS Before CLK CS Low Time CS High Time
See Test Circuits
See Test Circuits
See Test Circuits fCLK = 2MHz (Note 4) VCLK = 0V
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
Note 2: Timing for all input signals is measured at 0.8V for a High-to-Low transition and at 2V for a Low-to-High transition. Note 3: Timing specification are guaranteed but not tested. Note 4: This is the minimum time required for valid data transfer.
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1329-10 DNL vs Code
1.0 0.8 0.6 0.4
DNL (LSB)
LTC1329-10 INL vs Code
1.0
TA = 25C VCC = 3.3V V(IOUT) = 0.45V
0.8 0.6 0.4
TA = 25C VCC = 3.3V V(IOUT) = 0.45V
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE
1392 G01
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE
1329 * TPC02
DNL (LSB)
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VCC = 3.3V, unless otherwise specified. (Notes 2, 3)
MIN
q q q q q q q q q q q q q q q
TYP
MAX 2
UNITS MHz ns ns ns ns ns ns ns ns ns
150 400 150 150 150 150 200 250 150 400 400 4550 400 400
ns ns ns ns ns
LTC1329-50 DNL vs Code
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE
1392 G03
TA = 25C VCC = 3.3V V(IOUT) = 0.45V
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LTC1329-10/ LTC1329-50/LTC1329A-50 TYPICAL PERFORMANCE CHARACTERISTICS
LTC1329-50 INL vs Code
1.0 0.8 0.6 0.4
INL (LSB)
FULL-SCALE IOUT ERROR (LSB)
FULL-SCALE IOUT ERROR (LSB)
TA = 25C VCC = 3.3V V(IOUT) = 0.45V
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE
1329 * TPC04
LTC1329-10/LTC1329-50 Bias Voltage Rejection (Full-Scale Current)
0.5 0.4
FULL-SCALE IOUT ERROR (LSB) ZERO-SCALE IOUT CURRENT (nA)
MAXIMUM IOUT BIAS VOLTAGE (V)
TA = 25C VCC = 3.3V
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -15 -12 -6 -3 0 -9 IOUT BIAS VOLTAGE (V) 3 6 LTC1329-10 LTC1329-50
PIN FUNCTIONS
IOUT (Pin 1): DAC Current Output. In 3.3V or 5V systems, the DAC current output can be biased from - 15V to 2V or - 15V to 2.5V respectively. VCC (Pin 2): Voltage Supply (2.7V VCC 6.5V). This supply must be kept free from noise and ripple by bypassing directly to the ground plane. SHDN (Pin 3): Shutdown. A logic low puts the chip into Shutdown mode. The digital setting for the DAC is retained. CLK (Pin 4): Shift Clock. This clock synchronizes the serial data in 3-wire mode. This pin has a Schmitt trigger input. CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low on this CS pin enables the LTC1329. Upon power-up, a logic high at CS puts the chip into pulse mode. If CS ever goes low, the chip is configured in 3-wire mode until the next power is cycled. GND (Pin 6): Ground. Ground should be tied directly to a ground plane. DIN (UP/DN)(Pin 7): Data Input. In 3-wire mode, the DAC data is shifted into DIN on the rising edge of CLK. In pulse mode, upon power-up a logic high at DIN puts the counter into increment-only mode. If DIN ever goes low, the
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1329 G07
LTC1329-10/LTC1329-50 FullScale Current vs Temperature
3 2 1 0 -1 LTC1329-10 -2 -3 VCC = 3.3V V(IOUT) = 0.45V 2
LTC1329-10/LTC1329-50 Supply Voltage Rejection
TA = 25C V(IOUT) = 0.45V 1 LTC1329-50
LTC1329-50
0
LTC1329-10
-1
0
10
40 30 50 20 TEMPERATURE (C)
60
70
-2
0
1
4 3 5 2 SUPPLY VOLTAGE (V)
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1329 G05
1329 G06
LTC1329-10/LTC1329-50 Bias Voltage Rejection (Zero-Scale Current)
50 40 30 20 10 0 -10 -20 -30 -40 -50 -15 -12 -6 -3 0 -9 IOUT BIAS VOLTAGE (V) 3 6 LTC1329-10 LTC1329-50
6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5
Maximum IOUT Bias Voltage vs Supply Voltage
TA = 25C IOUT = FULL-SCALE CURRENT
2.7 3.2
3.7 4.2 4.7 5.2 5.7 SUPPLY VOLTAGE (V)
6.2
6.7
1329 G08
1329 * TPC09
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LTC1329-10/ LTC1329-50/LTC1329A-50
PIN FUNCTIONS
counter is configured in increment/decrement mode until the power is cycled. DOUT (Pin 8): Data Output. In 3-wire mode, on every conversion DOUT serially outputs the previous 8-bit DAC data. In pulse mode, DOUT is three-stated.
BLOCK DIAGRA
POWER-ON RESET
CLK DIN (UP/DN) CS SHDN CONTROL LOGIC
TEST CIRCUITS
Voltage Waveforms for tDO
CLK 0.8V t DO DOUT 2.4V 0.4V
1329 TC03
Load Circuit for t DO
1.4V 3k DOUT 100pF
1329 TC01
W
U
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LATCH AND LOGIC UP ONLY/ UP/DN
VOLTAGE REFERENCE SHDN V CC
LATCH AND LOGIC MODE SELECT 0 = PULSE 1 = 3-WIRE
SHDN
8-BIT CURRENT DAC
IOUT
8
CLK 8-BIT DAC REGISTER/COUNTER UP/DN 8 8
CLK 9-BIT SHIFT REGISTER DIN DOUT DOUT
1329 BD
Voltage Waveforms for t DZ, tDV
CS 2.0V 0.8V
2.4V DOUT HI-Z SET HIGH DOUT HI-Z SET LOW t DV 0.4V t DZ
90% HI-Z HI-Z 10%
1329 TC04
Load Circuit for t DZ, t DV
3k DOUT 100pF
5V t DZ WAVEFORM 2, t DV t DZ WAVEFORM 1
1329 TC02
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LTC1329-10/ LTC1329-50/LTC1329A-50
SERIAL I/O OPERATI G SEQUE CE
tCSLO CS tCKS CLK tCSS DIN D7 tDV DOUT Hi-Z D7 D6 D5 D4 D3 D6 D5 tDS D4 tDH D3 tDO D2 D1 D0 D2 D1 tCKLO D0 tDZ D7 Hi-Z
1329 F01
Figure 1. 3-Wire Interface Timing Specification
APPLICATIONS INFORMATION
8-BIT CURRENT OUTPUT DAC The LTC1329-10/LTC1329-50/LTC1329A-50 are 8-bit, current output digital-to-analog (DAC) converters. For each part, the 8-bit DAC output is guaranteed monotonic and is digitally adjustable in 256 equal steps. Upon power up, the internal DAC register resets to 10000000B and the DAC output assumes midrange. The current output (IOUT) can be biased from - 15V to 2V or - 15V to 2.5V in 3.3V and 5V systems, respectively. The LTC1329-10 features a fullscale output of 10A trimmed to 3% at room temperature (5% over temperature), while the LTC1329-50 features a 50A full scale and two accuracy grades; 1% at room temperature (2% over temperature) for the LTC1329A-50 and 3% at room temperature (5% over temperature) for the LTC1329-50. All versions include a flexible serial digital interface which allows easy interconnection to a variety of digital systems. DIGITAL INTERFACE Automatic Mode Selection The LTC1329 family includes a serial interface capable of communicating with the host system using one of three protocols; standard 3-wire mode, a 2-wire up/down pulse mode and a 1-wire increment-only pulse mode. The LTC1329 family is designed to auto-configure itself depending on the way data is presented to it. A diagram illustrating this auto detection behavior is shown in Figure 2. At power-up, the interface is set to 1-wire pulse mode. If the CS line ever goes low (as it will at the beginning of a valid 3-wire serial transfer) the chip immediately reconfigures itself into 3-wire mode and remains in this mode until the next time the power is cycled. If CS stays high, the LTC1329 family stays in pulse mode and watches the UP/DN pin to determine whether to switch to 2-wire mode. If UP/DN ever goes low (as it will the first time a "down" command is given) the chip switches into 2-wire pulse mode and remains in this mode until the next time the power is cycled. In a properly configured 1-wire system, CS and UP/DN will stay high continuously and the LTC1329-10/LTC1329-50/LTC1329A-50 will remain in 1wire pulse mode. 2-wire pulse mode systems should give a single "down" pulse sometime before the first data pulses are sent to prevent the LTC1329 family from staying in 1-wire mode if the first several pulses happen to be "ups".
POWER-UP CS GOES LOW CS STAYS HIGH
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tCSHI
tCKHI
tCSH
tCKH
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3-WIRE MODE DIN (UP/DN) GOES LOW
PULSE MODE DIN STAYS HIGH
INCREMENT/ DECREMENT
INCREMENTONLY
1329 F02
Figure 2. LTC1329 Operating Modes
LTC1329-10/ LTC1329-50/LTC1329A-50
APPLICATIONS INFORMATION
Standard 3-Wire Mode (Figure 3) Refer to the Serial Interface Operating Sequence in Figure 1. When operating in 3-wire mode, the LTC1329-10/ LTC1329-50/LTC1329A-50 will interface directly with most standard 3- or 4-wire serial interface systems. The clock (CLK) input synchronizes the data transfer with each input bit captured at the rising edge of CLK and each output data bit shifted out through DOUT at the falling edge. A falling edge at CS initiates the data transfer and brings the DOUT pin out of three-state. The serial 8-bit data representing the new DAC setting is shifted into the DIN pin. Simultaneously, the previous DAC setting is shifted out of the DOUT pin. After the new data is shifted in, a rising edge at CS transfers the data from the input shift register into the DAC register. The DAC output assumes the new value and the DOUT pin returns to a high-impedance state. IOUT = (B7 B6 B5 B4 B3 B2 B1 B0)IFULLSCALE/255
IOUT VCC 0.1F SHDN CLK CS DIN DOUT DIN AND DOUT CAN BE TIED TOGETHER FOR HALF DUPLEX DATA TRANSFER
1329 F03
1 2
IOUT VCC
DOUT DIN LTC1329
8 7
3 4
SHDN CLK
GND CS
6 5
Figure 3. 3-Wire Mode; Serial Interface (3-Wire Control by CS, CLK and DIN)
1-Wire Interface (Pulse Mode, Figure 4) In 1-wire pulse mode, each rising edge at CLK increments the upper six bits of the DAC register by one count. When incramented beyond 11111100B, the counter rolls over and sets the DAC to the minimum value (00000000B). In this way, a single pulse applied to CLK increases the DAC output by a single 4-LSB step and 63 pulses decrease the DAC output by one step. The last two LSBs are always zero in pulse mode. IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 To configure the LTC1329-10/LTC1329-50/LTC1329A-50 in 1-wire pulse mode, tie both the CS and DIN pins to VCC.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
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IOUT VCC 0.1F SHDN CLK
1 2
IOUT VCC
DOUT DIN LTC1329
8 7
3 4
SHDN CLK
GND CS
6 5
1329 F04
Figure 4. Pulse Mode: Increment Only (1-Wire Control by CLK)
2-Wire Interface (Pulse Mode, Figure 5) In 2-wire pulse mode, a logic HIGH at UP/DN programs the DAC register to increment and each rising edge at CLK increments the upper six bits of the register by one count. Similarly, a logic LOW at UP/DN set the DAC register to decrement and a rising edge at CLK decrements the upper six bits of the register by one count. Each count in 2-wire mode changes the DAC output by a single four LSB step. The DAC register stops incramenting at 11111100B and stops decrementing at 00000000B and will not roll over in 2-wire pulse mode. The last two LSBs are always zero in pulse mode. IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 To configure the LTC1329-10/LTC1329-50/LTC1329A-50 in 2-wire pulse mode, tie CS to VCC and bring the UP/DN pin low at least once during power-up.
1 2 8 7
IOUT VCC 0.1F SHDN CLK UP/DN
IOUT VCC
DOUT DIN LTC1329
3 4
SHDN CLK
GND CS
6 5
1329 TA04
Figure 5. Pulse Mode; Increment/Decrement (2-Wire Control by CLK and UP/DN)
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LTC1329-10/ LTC1329-50/LTC1329A-50
PACKAGE DESCRIPTIO
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP
0.014 - 0.019 (0.355 - 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 0.406 - 1.270
TYPICAL APPLICATIONS
Pulse Mode: Increment-Only (1-Wire Control by CLK) with Voltage Output
RFB 100k VOUT 6 VCC 7
LT1006 4 VEE
VOUT = (-IOUT)(RFB + VBIAS) VEE < VBIAS + VOUT
Digitally Controlled Power Supply Adjustment
VIN 3V 47 ILIM 47F LT1107 GND VIN SW1 FB SW2 L1* 33H VOUT 5V (150mA) TO 30V (14mA) 100F 3 4 22k 1 2 IOUT VCC DOUT DIN 8 7 MPU (e.g., 8051)
1N5817 510k
+
*COILTRONICS CTX33-4
RELATED PARTS
PART NUMBER LTC1451 LTC1452 LTC8043 DESCRIPTION 12-Bit Micropower Serial Input VOUT DAC 12-Bit Multiplying Serial Input VOUT DAC 12-Bit Multiplying Serial Input IOUT DAC COMMENTS Higher Resolution, 8-Pin SO Higher Resolution, 8-Pin SO Higher Resolution, 8-Pin SO
1329f LT/TP 0297 5K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
8 0.189 - 0.197* (4.801 - 5.004) 7 6 5
0.004 - 0.010 (0.101 - 0.254)
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
0.050 (1.270) TYP
1
2
3
4
SO8 0996
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2
1 2
IOUT VCC
DOUT DIN LTC1329
8 7
VBIAS 3
0.1F SHDN CLK 3 4
SHDN CLK
GND CS
6 5
FOR VCC = 3.3V, -15V VBIAS 2V FOR VCC = 5V, -15V VBIAS 2.5V
1329 TA02
+
LTC1329-50 SHDN CLK GND CS 6 5
P1.2 P1.1 P1.0
1329 TA03
(c) LINEAR TECHNOLOGY CORPORATION 1997

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